1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that performs a refresh operation in response to a refresh command supplied from outside.
2. Description of Related Art
A DRAM (Dynamic Random Access Memory) that is one of representative semiconductor devices stores therein information by electric charge charged in cell capacitors. Because the electric charge charged in the cell capacitors decays with a passage of time by a leakage current, it is necessary to perform a refresh operation at regular intervals so as to correctly hold the information. In the case of the DRAM, it is specified that information-holding time of the cell capacitors is equal to or longer than 64 ms according to the standards. Therefore, it suffices that the DRAM performs a refresh operation on all memory cells within a 64-ms period.
The information-holding time of the cell capacitors depends on temperature and tends to be longer at a lower temperature. Therefore, a refresh cycle can be set longer than 64 ms in a low temperature state, which can thereby reduce power consumption. For example, Japanese Patent Application Laid-open No. 2007-310983 discloses a technique of changing a cycle of generating an internal refresh signal according to temperature information in a self-refresh mode.
However, the technique disclosed in Japanese Patent Application Laid-open No. 2007-310983 has the following problems. Although power consumption can be reduced in the self-refresh mode, it is impossible to reduce power consumption in an auto-refresh mode in which a refresh operation is performed in response to a refresh command input from outside.
Meanwhile, Japanese Patent Application Laid-open No. 2007-188635 discloses a technique of executing one refresh operation whenever an auto-refresh command is input n times, where n is an integer, from outside. However, the method described in Japanese Patent Application Laid-open No. 2007-188635 has the following problems. An adjusted refresh cycle is n times longer than (an integer multiple of) the period (64 ms) specified according to the standards. Therefore, the refresh cycle cannot be finely adjusted. Furthermore, setting of a value of the n is made in response to a command from a fuse trimming unit or controller in manufacturing phase. Accordingly, for example, even if chip temperature changes, the refresh cycle cannot be automatically adjusted in a DRAM.
The conventional problems occur to not only the DRAM but also all other semiconductor devices that perform refresh operations in response to a refresh command input from outside of the devices. Moreover, the conventional problems occur similarly to a case of adjusting a refresh cycle in response to a change in the information holding time for reasons other than the reason related to temperatures.